APA (7th ed.) Citation

Rubia, J. J., & Sathish Kumar, G. (2020). A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm. International Journal of Electrical Engineering Education, 57(4), 361. https://doi.org/10.1177/0020720918813836

Chicago Style (17th ed.) Citation

Rubia, J Jency, and GA Sathish Kumar. "A High-speed Fixed Width Floating-point Multiplier Using Residue Logarithmic Number System Algorithm." International Journal of Electrical Engineering Education 57, no. 4 (2020): 361. https://doi.org/10.1177/0020720918813836.

MLA (9th ed.) Citation

Rubia, J Jency, and GA Sathish Kumar. "A High-speed Fixed Width Floating-point Multiplier Using Residue Logarithmic Number System Algorithm." International Journal of Electrical Engineering Education, vol. 57, no. 4, 2020, p. 361, https://doi.org/10.1177/0020720918813836.