A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm.
Saved in:
| Title: | A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm. |
|---|---|
| Authors: | Rubia, J Jency1 (AUTHOR) jencyrubia@gmail.com, Sathish Kumar, GA1 (AUTHOR) |
| Source: | International Journal of Electrical Engineering Education. Oct2020, Vol. 57 Issue 4, p361-375. 15p. 1 Diagram, 2 Charts, 3 Graphs. |
| Subject Terms: | *Algorithms, Number systems, Digital signal processing, Integrating circuits, Multipliers (Mathematical analysis), Scientific computing, Artificial neural networks |
| Abstract: | The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the processing speed. The truncation errors were reduced by using Taylor series. RLNS is the combination of both the residue number system and the logarithmic number system, and uses a table lookup including all bits for expansion. The proposed scheme is effective with regard to speed, area and power utilization in contrast to the design of conservative Floating-Point mathematics designs. Synthesis results were obtained using a Xilinx 14.7 ISE simulator. The area is 16,668 µm2, power is 37 mW, delay is 6.160 ns and truncation error can be lessened by 89% as compared with the direct-truncated multiplier. The proposed Fixed Width RLNS multiplier performs with lesser compensation error and with minimal hardware complexity, particularly as multiplier input bits increment. [ABSTRACT FROM AUTHOR] |
| Copyright of International Journal of Electrical Engineering Education is the property of Sage Publications Inc. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Education Research Complete |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
|---|---|
| Header | DbId: ehh DbLabel: Education Research Complete An: 144891378 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Rubia%2C+J+Jency%22">Rubia, J Jency</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> jencyrubia@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Sathish+Kumar%2C+GA%22">Sathish Kumar, GA</searchLink><relatesTo>1</relatesTo> (AUTHOR) – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Electrical+Engineering+Education%22">International Journal of Electrical Engineering Education</searchLink>. Oct2020, Vol. 57 Issue 4, p361-375. 15p. 1 Diagram, 2 Charts, 3 Graphs. – Name: Subject Label: Subject Terms Group: Su Data: *<searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Number+systems%22">Number systems</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+signal+processing%22">Digital signal processing</searchLink><br /><searchLink fieldCode="DE" term="%22Integrating+circuits%22">Integrating circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Multipliers+%28Mathematical+analysis%29%22">Multipliers (Mathematical analysis)</searchLink><br /><searchLink fieldCode="DE" term="%22Scientific+computing%22">Scientific computing</searchLink><br /><searchLink fieldCode="DE" term="%22Artificial+neural+networks%22">Artificial neural networks</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the processing speed. The truncation errors were reduced by using Taylor series. RLNS is the combination of both the residue number system and the logarithmic number system, and uses a table lookup including all bits for expansion. The proposed scheme is effective with regard to speed, area and power utilization in contrast to the design of conservative Floating-Point mathematics designs. Synthesis results were obtained using a Xilinx 14.7 ISE simulator. The area is 16,668 µm2, power is 37 mW, delay is 6.160 ns and truncation error can be lessened by 89% as compared with the direct-truncated multiplier. The proposed Fixed Width RLNS multiplier performs with lesser compensation error and with minimal hardware complexity, particularly as multiplier input bits increment. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of International Journal of Electrical Engineering Education is the property of Sage Publications Inc. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=ehh&AN=144891378 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1177/0020720918813836 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 15 StartPage: 361 Subjects: – SubjectFull: Algorithms Type: general – SubjectFull: Number systems Type: general – SubjectFull: Digital signal processing Type: general – SubjectFull: Integrating circuits Type: general – SubjectFull: Multipliers (Mathematical analysis) Type: general – SubjectFull: Scientific computing Type: general – SubjectFull: Artificial neural networks Type: general Titles: – TitleFull: A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Rubia, J Jency – PersonEntity: Name: NameFull: Sathish Kumar, GA IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Text: Oct2020 Type: published Y: 2020 Identifiers: – Type: issn-print Value: 00207209 Numbering: – Type: volume Value: 57 – Type: issue Value: 4 Titles: – TitleFull: International Journal of Electrical Engineering Education Type: main |
| ResultId | 1 |
