Low-Power Direct Hardware Implementation of Logic Controllers Using Standard Languages.
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| Title: | Low-Power Direct Hardware Implementation of Logic Controllers Using Standard Languages. |
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| Authors: | Milik, Adam1 (AUTHOR) adam.milik@polsl.pl, Kierat, Wojciech1 (AUTHOR), Rudnicki, Tomasz1 (AUTHOR) |
| Source: | Energies (19961073). Apr2026, Vol. 19 Issue 8, p2001. 27p. |
| Subject Terms: | *Programmable controllers, *Field programmable gate arrays, *Parallel programming, *Programming languages, *Energy conservation |
| Abstract: | The paper shows the methodologies of implementing a high-performance low-power logic control system designed with the use of standard languages like LD and SFC (according to the IEC61131-3 standard) directly in hardware utilizing FPGA devices. The essential idea is to convert the sequential sentences of a language to parallel computations and then map them to a dedicated hardware structure. The flexible graph-based method of language mapping is shown. It enables extracting control and data flow from language sentences. The direct hardware mapping technique enables building not only a high-performance structures but also a low-power implementations. All implementations retain a very short response time consisting of several clock cycles (from 3 to 7). The proposed low-power mapping strategies enable power saving up to 10 times while retaining processing performance. The obtained results are compared with a standard implementation using a benchmark program set. The paper is concluded with a comparison of the performance and energy consumption for the proposed implementation strategies. [ABSTRACT FROM AUTHOR] |
| Database: | Energy & Power Source |
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| FullText | Links: – Type: pdflink Text: Availability: 1 |
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| Header | DbId: enr DbLabel: Energy & Power Source An: 193438341 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Low-Power Direct Hardware Implementation of Logic Controllers Using Standard Languages. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Milik%2C+Adam%22">Milik, Adam</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> adam.milik@polsl.pl</i><br /><searchLink fieldCode="AR" term="%22Kierat%2C+Wojciech%22">Kierat, Wojciech</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Rudnicki%2C+Tomasz%22">Rudnicki, Tomasz</searchLink><relatesTo>1</relatesTo> (AUTHOR) – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Energies+%2819961073%29%22">Energies (19961073)</searchLink>. Apr2026, Vol. 19 Issue 8, p2001. 27p. – Name: Subject Label: Subject Terms Group: Su Data: *<searchLink fieldCode="DE" term="%22Programmable+controllers%22">Programmable controllers</searchLink><br />*<searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br />*<searchLink fieldCode="DE" term="%22Parallel+programming%22">Parallel programming</searchLink><br />*<searchLink fieldCode="DE" term="%22Programming+languages%22">Programming languages</searchLink><br />*<searchLink fieldCode="DE" term="%22Energy+conservation%22">Energy conservation</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The paper shows the methodologies of implementing a high-performance low-power logic control system designed with the use of standard languages like LD and SFC (according to the IEC61131-3 standard) directly in hardware utilizing FPGA devices. The essential idea is to convert the sequential sentences of a language to parallel computations and then map them to a dedicated hardware structure. The flexible graph-based method of language mapping is shown. It enables extracting control and data flow from language sentences. The direct hardware mapping technique enables building not only a high-performance structures but also a low-power implementations. All implementations retain a very short response time consisting of several clock cycles (from 3 to 7). The proposed low-power mapping strategies enable power saving up to 10 times while retaining processing performance. The obtained results are compared with a standard implementation using a benchmark program set. The paper is concluded with a comparison of the performance and energy consumption for the proposed implementation strategies. [ABSTRACT FROM AUTHOR] |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=enr&AN=193438341 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.3390/en19082001 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 27 StartPage: 2001 Subjects: – SubjectFull: Programmable controllers Type: general – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Parallel programming Type: general – SubjectFull: Programming languages Type: general – SubjectFull: Energy conservation Type: general Titles: – TitleFull: Low-Power Direct Hardware Implementation of Logic Controllers Using Standard Languages. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Milik, Adam – PersonEntity: Name: NameFull: Kierat, Wojciech – PersonEntity: Name: NameFull: Rudnicki, Tomasz IsPartOfRelationships: – BibEntity: Dates: – D: 15 M: 04 Text: Apr2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 19961073 Numbering: – Type: volume Value: 19 – Type: issue Value: 8 Titles: – TitleFull: Energies (19961073) Type: main |
| ResultId | 1 |
