p88110: A Graphical Simulator for Computer Architecture and Organization Courses
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| Title: | p88110: A Graphical Simulator for Computer Architecture and Organization Courses |
|---|---|
| Language: | English |
| Authors: | Garcia, M. I., Rodriguez, S., Perez, A., Garcia, A. |
| Source: | IEEE Transactions on Education. May 2009 52(2):248-256. |
| Availability: | Institute of Electrical and Electronics Engineers, Inc. 445 Hoes Lane, Piscataway, NJ 08854. Tel: 732-981-0060; Web site: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=13 |
| Peer Reviewed: | Y |
| Page Count: | 9 |
| Publication Date: | 2009 |
| Document Type: | Journal Articles Reports - Descriptive |
| Education Level: | Higher Education |
| Descriptors: | Assignments, Client Server Architecture, Simulation, Active Learning, Laboratories, Computers, Foreign Countries, Memory, Evaluation, Enrollment, Higher Education, Computer System Design, Computer Science Education, Technical Education |
| Geographic Terms: | Spain |
| DOI: | 10.1109/TE.2008.927690 |
| ISSN: | 0018-9359 |
| Abstract: | Studying fundamental Computer Architecture and Organization topics requires a significant amount of practical work if students are to acquire a good grasp of the theoretical concepts presented in classroom lectures or textbooks. The use of simulators is commonly adopted in order to reach this objective. However, as most of the available educational simulators focus on specific topics, different laboratory assignments usually require the use of different simulators. This paper presents a graphical and interactive reduced instruction set computer (RISC) processor and memory simulator that allows active learning of some theoretical concepts covered in Computer Architecture and Organization courses. The simulator can be configured to present different processor views, from a simple serial one, without caches or pipelines, to a more realistic one with caches and superscalar execution. This approach allows a set of increasingly complex code-based laboratory assignments to be developed using a single simulator, covering topics ranging from assembly language programming to the analysis of the different kind of cache misses, pipeline hazards or branch prediction hits and misses produced during a program execution. The simulator has been included in a an automatic assessment system that helps the students to complete the assignments and helps teachers to evaluate the correctness of the students' solutions in different environments, such as high-enrollment courses or distance education. Since 1996, both the simulator and the automatic assessment system have been successfully used by more than 5000 students in Computer Architecture and Organization courses at the Technical University of Madrid (UPM), Spain. (Contains 1 table and 10 figures.) |
| Abstractor: | As Provided |
| Number of References: | 20 |
| Entry Date: | 2010 |
| Accession Number: | EJ890179 |
| Database: | ERIC |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: eric DbLabel: ERIC An: EJ890179 AccessLevel: 3 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: p88110: A Graphical Simulator for Computer Architecture and Organization Courses – Name: Language Label: Language Group: Lang Data: English – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Garcia%2C+M%2E+I%2E%22">Garcia, M. I.</searchLink><br /><searchLink fieldCode="AR" term="%22Rodriguez%2C+S%2E%22">Rodriguez, S.</searchLink><br /><searchLink fieldCode="AR" term="%22Perez%2C+A%2E%22">Perez, A.</searchLink><br /><searchLink fieldCode="AR" term="%22Garcia%2C+A%2E%22">Garcia, A.</searchLink> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="SO" term="%22IEEE+Transactions+on+Education%22"><i>IEEE Transactions on Education</i></searchLink>. May 2009 52(2):248-256. – Name: Avail Label: Availability Group: Avail Data: Institute of Electrical and Electronics Engineers, Inc. 445 Hoes Lane, Piscataway, NJ 08854. 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The use of simulators is commonly adopted in order to reach this objective. However, as most of the available educational simulators focus on specific topics, different laboratory assignments usually require the use of different simulators. This paper presents a graphical and interactive reduced instruction set computer (RISC) processor and memory simulator that allows active learning of some theoretical concepts covered in Computer Architecture and Organization courses. The simulator can be configured to present different processor views, from a simple serial one, without caches or pipelines, to a more realistic one with caches and superscalar execution. This approach allows a set of increasingly complex code-based laboratory assignments to be developed using a single simulator, covering topics ranging from assembly language programming to the analysis of the different kind of cache misses, pipeline hazards or branch prediction hits and misses produced during a program execution. The simulator has been included in a an automatic assessment system that helps the students to complete the assignments and helps teachers to evaluate the correctness of the students' solutions in different environments, such as high-enrollment courses or distance education. Since 1996, both the simulator and the automatic assessment system have been successfully used by more than 5000 students in Computer Architecture and Organization courses at the Technical University of Madrid (UPM), Spain. (Contains 1 table and 10 figures.) – Name: AbstractInfo Label: Abstractor Group: Ab Data: As Provided – Name: Ref Label: Number of References Group: RefInfo Data: 20 – Name: DateEntry Label: Entry Date Group: Date Data: 2010 – Name: AN Label: Accession Number Group: ID Data: EJ890179 |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=eric&AN=EJ890179 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TE.2008.927690 Languages: – Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 248 Subjects: – SubjectFull: Assignments Type: general – SubjectFull: Client Server Architecture Type: general – SubjectFull: Simulation Type: general – SubjectFull: Active Learning Type: general – SubjectFull: Laboratories Type: general – SubjectFull: Computers Type: general – SubjectFull: Foreign Countries Type: general – SubjectFull: Memory Type: general – SubjectFull: Evaluation Type: general – SubjectFull: Enrollment Type: general – SubjectFull: Higher Education Type: general – SubjectFull: Computer System Design Type: general – SubjectFull: Computer Science Education Type: general – SubjectFull: Technical Education Type: general – SubjectFull: Spain Type: general Titles: – TitleFull: p88110: A Graphical Simulator for Computer Architecture and Organization Courses Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Garcia, M. I. – PersonEntity: Name: NameFull: Rodriguez, S. – PersonEntity: Name: NameFull: Perez, A. – PersonEntity: Name: NameFull: Garcia, A. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 05 Type: published Y: 2009 Identifiers: – Type: issn-print Value: 0018-9359 Numbering: – Type: volume Value: 52 – Type: issue Value: 2 Titles: – TitleFull: IEEE Transactions on Education Type: main |
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