APA (7th ed.) Citation

X, J., X, J., S, W., Y, G., F, G., X, L., . . . M, L. (2024). A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM. Micromachines, 15(5), . https://doi.org/10.3390/mi15050557

Chicago Style (17th ed.) Citation

X, Jiang, Jia X, Wang S, Guo Y, Guo F, Long X, Geng L, Yang J, and Liu M. "A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM." Micromachines 15, no. 5 (2024). https://doi.org/10.3390/mi15050557.

MLA (9th ed.) Citation

X, Jiang, et al. "A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM." Micromachines, vol. 15, no. 5, 2024, https://doi.org/10.3390/mi15050557.