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A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.

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Title: A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.
Authors: Jiang X; Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China.; School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100029, China.; Xi'an UniIC Semiconductors, Xi'an 710075, China., Jia X; Xi'an UniIC Semiconductors, Xi'an 710075, China.; School of Microelectronics, Xi'an Jiaotong University, Xianning West Road 28#, Xi'an 710049, China., Wang S; Xi'an UniIC Semiconductors, Xi'an 710075, China., Guo Y; Xi'an UniIC Semiconductors, Xi'an 710075, China., Guo F; Xi'an UniIC Semiconductors, Xi'an 710075, China., Long X; Xi'an UniIC Semiconductors, Xi'an 710075, China., Geng L; School of Microelectronics, Xi'an Jiaotong University, Xianning West Road 28#, Xi'an 710049, China., Yang J; School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100029, China., Liu M; Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China.; School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100029, China.
Source: Micromachines [Micromachines (Basel)] 2024 Apr 23; Vol. 15 (5). Date of Electronic Publication: 2024 Apr 23.
Publication Type: Journal Article
Journal Info: Publisher: MDPI Country of Publication: Switzerland NLM ID: 101640903 Publication Model: Electronic Cited Medium: Print ISSN: 2072-666X (Print) Linking ISSN: 2072666X NLM ISO Abbreviation: Micromachines (Basel) Subsets: PubMed not MEDLINE
Database: MEDLINE Ultimate
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  Data: A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.
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  Data: <searchLink fieldCode="AU" term="%22Jiang+X%22">Jiang X</searchLink>; Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China.; School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100029, China.; Xi'an UniIC Semiconductors, Xi'an 710075, China.<br /><searchLink fieldCode="AU" term="%22Jia+X%22">Jia X</searchLink>; Xi'an UniIC Semiconductors, Xi'an 710075, China.; School of Microelectronics, Xi'an Jiaotong University, Xianning West Road 28#, Xi'an 710049, China.<br /><searchLink fieldCode="AU" term="%22Wang+S%22">Wang S</searchLink>; Xi'an UniIC Semiconductors, Xi'an 710075, China.<br /><searchLink fieldCode="AU" term="%22Guo+Y%22">Guo Y</searchLink>; Xi'an UniIC Semiconductors, Xi'an 710075, China.<br /><searchLink fieldCode="AU" term="%22Guo+F%22">Guo F</searchLink>; Xi'an UniIC Semiconductors, Xi'an 710075, China.<br /><searchLink fieldCode="AU" term="%22Long+X%22">Long X</searchLink>; Xi'an UniIC Semiconductors, Xi'an 710075, China.<br /><searchLink fieldCode="AU" term="%22Geng+L%22">Geng L</searchLink>; School of Microelectronics, Xi'an Jiaotong University, Xianning West Road 28#, Xi'an 710049, China.<br /><searchLink fieldCode="AU" term="%22Yang+J%22">Yang J</searchLink>; School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100029, China.<br /><searchLink fieldCode="AU" term="%22Liu+M%22">Liu M</searchLink>; Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China.; School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100029, China.
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  Data: <searchLink fieldCode="JN" term="%22101640903%22">Micromachines</searchLink> [Micromachines (Basel)] 2024 Apr 23; Vol. 15 (5). <i>Date of Electronic Publication: </i>2024 Apr 23.
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        Value: 10.3390/mi15050557
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      – TitleFull: A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM.
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              Text: 2024 Apr 23
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