APA (7th ed.) Citation

Kumar, A., Beeraka, S. M., Singh, J., & Gupta, B. (2023). An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications. Circuits, Systems & Signal Processing, 42(5), 2828. https://doi.org/10.1007/s00034-022-02237-7

Chicago Style (17th ed.) Citation

Kumar, Abhash, Sai Manohar Beeraka, Jawar Singh, and Bharat Gupta. "An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications." Circuits, Systems & Signal Processing 42, no. 5 (2023): 2828. https://doi.org/10.1007/s00034-022-02237-7.

MLA (9th ed.) Citation

Kumar, Abhash, et al. "An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications." Circuits, Systems & Signal Processing, vol. 42, no. 5, 2023, p. 2828, https://doi.org/10.1007/s00034-022-02237-7.