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Verification Techniques for System-Level Design

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Title: Verification Techniques for System-Level Design
Description: This book will explain how to verify SoC (Systems on Chip) logic designs using'formal and'semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in'functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. - First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs - Formal verification of high-level designs (RTL or higher) - Verification techniques are discussed with associated system-level design methodology
Authors: Masahiro Fujita, Indradeep Ghosh, Mukul Prasad
Resource Type: eBook.
Subjects: Formal methods (Computer science), Integrated circuits--Verification, Systems on a chip--Testing
Categories: COMPUTERS / Computer Architecture, TECHNOLOGY & ENGINEERING / Industrial Design / Product
Database: eBook Collection (EBSCOhost)
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  – Type: ebook-pdf
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  Availability: 0
Header DbId: nlebk
DbLabel: eBook Collection (EBSCOhost)
An: 210385
RelevancyScore: 1018
AccessLevel: 6
PubType: eBook
PubTypeId: ebook
PreciseRelevancyScore: 1018.08020019531
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  Data: Verification Techniques for System-Level Design
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  Label: Description
  Group: Ab
  Data: This book will explain how to verify SoC (Systems on Chip) logic designs using'formal and'semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in'functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. - First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs - Formal verification of high-level designs (RTL or higher) - Verification techniques are discussed with associated system-level design methodology
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  Data: <searchLink fieldCode="AR" term="%22Masahiro+Fujita%22">Masahiro Fujita</searchLink><br /><searchLink fieldCode="AR" term="%22Indradeep+Ghosh%22">Indradeep Ghosh</searchLink><br /><searchLink fieldCode="AR" term="%22Mukul+Prasad%22">Mukul Prasad</searchLink>
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  Data: eBook.
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  Data: <searchLink fieldCode="DE" term="%22Formal+methods+%28Computer+science%29%22">Formal methods (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits--Verification%22">Integrated circuits--Verification</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+on+a+chip--Testing%22">Systems on a chip--Testing</searchLink>
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RecordInfo BibRecord:
  BibEntity:
    Classifications:
      – Code: 621.3815
        Scheme: ddc
        Type: prePub
    Languages:
      – Code: eng
        Text: English
    Subjects:
      – SubjectFull: Formal methods (Computer science)
        Type: general
      – SubjectFull: Integrated circuits--Verification
        Type: general
      – SubjectFull: Systems on a chip--Testing
        Type: general
    Titles:
      – TitleFull: Verification Techniques for System-Level Design
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Masahiro Fujita
      – PersonEntity:
          Name:
            NameFull: Indradeep Ghosh
      – PersonEntity:
          Name:
            NameFull: Mukul Prasad
      – PersonEntity:
          Name:
            NameFull: Masahiro Fujita
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            NameFull: Indradeep Ghosh
      – PersonEntity:
          Name:
            NameFull: Mukul Prasad
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          Dates:
            – D: 01
              M: 01
              Type: published
              Y: 2008
            – D: 04
              M: 02
              Type: profile
              Y: 2014
          Identifiers:
            – Type: isbn-print
              Value: 9780123706164
            – Type: isbn-electronic
              Value: 9780080553139
          Titles:
            – TitleFull: Verification Techniques for System-Level Design
              Type: main
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