System-on-Chip Test Architectures : Nanometer Design for Testability
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| Title: | System-on-Chip Test Architectures : Nanometer Design for Testability |
|---|---|
| Description: | Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. - Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. - Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. - Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. - Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. - Practical problems at the end of each chapter for students. |
| Authors: | Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| Resource Type: | eBook. |
| Subjects: | Integrated circuits--Very large scale integration--Design, Integrated circuits--Very large scale integration--Testing, Systems on a chip--Testing |
| Categories: | TECHNOLOGY & ENGINEERING / Industrial Design / Product, TECHNOLOGY & ENGINEERING / Electrical |
| Database: | eBook Collection (EBSCOhost) |
| FullText | Links: – Type: ebook-pdf Text: Availability: 0 |
|---|---|
| Header | DbId: nlebk DbLabel: eBook Collection (EBSCOhost) An: 214796 RelevancyScore: 1018 AccessLevel: 6 PubType: eBook PubTypeId: ebook PreciseRelevancyScore: 1018.08020019531 |
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| Items | – Name: Title Label: Title Group: Ti Data: System-on-Chip Test Architectures : Nanometer Design for Testability – Name: Abstract Label: Description Group: Ab Data: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. - Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. - Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. - Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. - Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. - Practical problems at the end of each chapter for students. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Laung-Terng+Wang%22">Laung-Terng Wang</searchLink><br /><searchLink fieldCode="AR" term="%22Charles+E%2E+Stroud%22">Charles E. Stroud</searchLink><br /><searchLink fieldCode="AR" term="%22Nur+A%2E+Touba%22">Nur A. Touba</searchLink> – Name: TypePub Label: Resource Type Group: TypPub Data: eBook. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Integrated+circuits--Very+large+scale+integration--Design%22">Integrated circuits--Very large scale integration--Design</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits--Very+large+scale+integration--Testing%22">Integrated circuits--Very large scale integration--Testing</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+on+a+chip--Testing%22">Systems on a chip--Testing</searchLink> – Name: SubjectBISAC Label: Categories Group: Su Data: <searchLink fieldCode="ZK" term="%22TECHNOLOGY+%26+ENGINEERING+%2F+Industrial+Design+%2F+Product%22">TECHNOLOGY & ENGINEERING / Industrial Design / Product</searchLink><br /><searchLink fieldCode="ZK" term="%22TECHNOLOGY+%26+ENGINEERING+%2F+Electrical%22">TECHNOLOGY & ENGINEERING / Electrical</searchLink> |
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| RecordInfo | BibRecord: BibEntity: Classifications: – Code: 621.395 Scheme: ddc Type: prePub Languages: – Code: eng Text: English Subjects: – SubjectFull: Integrated circuits--Very large scale integration--Design Type: general – SubjectFull: Integrated circuits--Very large scale integration--Testing Type: general – SubjectFull: Systems on a chip--Testing Type: general Titles: – TitleFull: System-on-Chip Test Architectures : Nanometer Design for Testability Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Laung-Terng Wang – PersonEntity: Name: NameFull: Charles E. Stroud – PersonEntity: Name: NameFull: Nur A. Touba – PersonEntity: Name: NameFull: Laung-Terng Wang – PersonEntity: Name: NameFull: Charles E. Stroud – PersonEntity: Name: NameFull: Nur A. Touba IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Type: published Y: 2008 – D: 04 M: 02 Type: profile Y: 2014 Identifiers: – Type: isbn-print Value: 9780123739735 – Type: isbn-electronic Value: 9780080556802 Titles: – TitleFull: System-on-Chip Test Architectures : Nanometer Design for Testability Type: main |
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