View in EDS

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS.

Saved in:
Bibliographic Details
Title: Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS.
Authors: Mammei, Enrico1, Loi, Fabrizio1, Radice, Francesco1, Dati, Angelo1, Bruccoleri, Melchiorre1, Bassi, Matteo1, Mazzanti, Andrea1
Source: IEEE Journal of Solid-State Circuits; Dec2014, Vol. 49 Issue 12, p3130-3140, 11p
Database: Applied Science & Technology Source
Description
ISSN:00189200
DOI:10.1109/JSSC.2014.2345770