Layered tile architecture for efficient hardware spiking neural networks.
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| Title: | Layered tile architecture for efficient hardware spiking neural networks. |
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| Authors: | Wan, Lei1, Liu, Junxiu1, liujunxiu@mailbox.gxnu.edu.cn, Harkin, Jim2, McDaid, Liam2, Luo, Yuling1 |
| Source: | Microprocessors & Microsystems; Aug2017, Vol. 53, p21-32, 12p |
| Database: | Applied Science & Technology Source |
| ISSN: | 01419331 |
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| DOI: | 10.1016/j.micpro.2017.07.005 |
