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Layered tile architecture for efficient hardware spiking neural networks.

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Bibliographic Details
Title: Layered tile architecture for efficient hardware spiking neural networks.
Authors: Wan, Lei1, Liu, Junxiu1, liujunxiu@mailbox.gxnu.edu.cn, Harkin, Jim2, McDaid, Liam2, Luo, Yuling1
Source: Microprocessors & Microsystems; Aug2017, Vol. 53, p21-32, 12p
Database: Applied Science & Technology Source
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  Availability: 0
Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 124935126
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1016/j.micpro.2017.07.005
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      – Code: eng
        Text: English
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        PageCount: 12
        StartPage: 21
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      – TitleFull: Layered tile architecture for efficient hardware spiking neural networks.
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            NameFull: Wan, Lei
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            NameFull: Liu, Junxiu
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            NameFull: Harkin, Jim
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            NameFull: McDaid, Liam
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              Text: Aug2017
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              Y: 2017
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              Value: 53
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