Efficient dual-precision floating-point fused-multiply-add architecture.
Saved in:
| Title: | Efficient dual-precision floating-point fused-multiply-add architecture. |
|---|---|
| Authors: | Arunachalam, V.1, varunachalam@vit.ac.in, Joseph Raj, Alex Noel2, Hampannavar, Naveen3, Bidul, C.B.4 |
| Source: | Microprocessors & Microsystems; Mar2018, Vol. 57, p23-31, 9p |
| Database: | Applied Science & Technology Source |
| ISSN: | 01419331 |
|---|---|
| DOI: | 10.1016/j.micpro.2017.12.009 |
