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Efficient dual-precision floating-point fused-multiply-add architecture.

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Title: Efficient dual-precision floating-point fused-multiply-add architecture.
Authors: Arunachalam, V.1, varunachalam@vit.ac.in, Joseph Raj, Alex Noel2, Hampannavar, Naveen3, Bidul, C.B.4
Source: Microprocessors & Microsystems; Mar2018, Vol. 57, p23-31, 9p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 127962099
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1016/j.micpro.2017.12.009
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      – Code: eng
        Text: English
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        PageCount: 9
        StartPage: 23
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      – TitleFull: Efficient dual-precision floating-point fused-multiply-add architecture.
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            NameFull: Joseph Raj, Alex Noel
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            NameFull: Hampannavar, Naveen
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              Text: Mar2018
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              Y: 2018
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              Value: 57
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