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Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization.

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Bibliographic Details
Title:	Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization.
Authors:	Tomar, Geetam Singh¹, George, Marcus Lloyde²
Source:	Wireless Personal Communications; Feb2018, Vol. 98 Issue 4, p3549-3561, 13p
Database:	Applied Science & Technology Source
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Description
ISSN:	09296212
DOI:	10.1007/s11277-017-5028-z