SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.
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| Title: | SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures. |
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| Authors: | Gao, Lan1, lan.gao@buaa.edu.cn, Wang, Rui1, wangrui@buaa.edu.cn, Xu, Yunlong2, Yang, Hailong1, Luan, Zhongzhi1, Qian, Depei1, Zhang, Han3, Cai, Jihong3 |
| Source: | Journal of Supercomputing; Jul2018, Vol. 74 Issue 7, p3388-3414, 27p |
| Database: | Applied Science & Technology Source |
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| ISSN: | 09208542 |
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| DOI: | 10.1007/s11227-018-2389-3 |
