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SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.

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Title: SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.
Authors: Gao, Lan1, lan.gao@buaa.edu.cn, Wang, Rui1, wangrui@buaa.edu.cn, Xu, Yunlong2, Yang, Hailong1, Luan, Zhongzhi1, Qian, Depei1, Zhang, Han3, Cai, Jihong3
Source: Journal of Supercomputing; Jul2018, Vol. 74 Issue 7, p3388-3414, 27p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 130553728
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.
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  Data: <searchLink fieldCode="AU" term="%22Gao%2C+Lan%22">Gao, Lan</searchLink><relatesTo>1</relatesTo>, <i>lan.gao@buaa.edu.cn</i><br /><searchLink fieldCode="AU" term="%22Wang%2C+Rui%22">Wang, Rui</searchLink><relatesTo>1</relatesTo>, <i>wangrui@buaa.edu.cn</i><br /><searchLink fieldCode="AU" term="%22Xu%2C+Yunlong%22">Xu, Yunlong</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AU" term="%22Yang%2C+Hailong%22">Yang, Hailong</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AU" term="%22Luan%2C+Zhongzhi%22">Luan, Zhongzhi</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AU" term="%22Qian%2C+Depei%22">Qian, Depei</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AU" term="%22Zhang%2C+Han%22">Zhang, Han</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AU" term="%22Cai%2C+Jihong%22">Cai, Jihong</searchLink><relatesTo>3</relatesTo>
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PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=130553728
RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1007/s11227-018-2389-3
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      – Code: eng
        Text: English
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        PageCount: 27
        StartPage: 3388
    Titles:
      – TitleFull: SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.
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            NameFull: Gao, Lan
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            NameFull: Wang, Rui
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            NameFull: Luan, Zhongzhi
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            NameFull: Qian, Depei
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            NameFull: Zhang, Han
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            – D: 01
              M: 07
              Text: Jul2018
              Type: published
              Y: 2018
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              Value: 74
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              Value: 7
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            – TitleFull: Journal of Supercomputing
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