High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.
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| Title: | High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. |
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| Authors: | Ueno, Rei1, ueno@riec.tohoku.ac.jp, Homma, Naofumi1, homma@riec.tohoku.ac.jp, Morioka, Sumio2, morioka@fb3.so-net.ne.jp, Miura, Noriyuki3, miura@cs.kobe-u.ac.jp, Matsuda, Kohei3, matsuda@cs.kobe-u.ac.jp, Nagata, Makoto3, nagata@cs.kobe-u.ac.jp, Bhasin, Shivam4, sbhasin@ntu.edu.sg, Mathieu, Yves5, yves.mathieu@telecom-paristech.fr, Graba, Tarik5, tarik.graba@telecom-paristech.fr, Danger, Jean-Luc5, jean-luc.danger@telecom-paristech.fr |
| Source: | IEEE Transactions on Computers; Apr2020, Vol. 69 Issue 4, p534-548, 15p |
| Database: | Applied Science & Technology Source |
| ISSN: | 00189340 |
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| DOI: | 10.1109/TC.2019.2957355 |
