High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.
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| Title: | High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. |
|---|---|
| Authors: | Ueno, Rei1, ueno@riec.tohoku.ac.jp, Homma, Naofumi1, homma@riec.tohoku.ac.jp, Morioka, Sumio2, morioka@fb3.so-net.ne.jp, Miura, Noriyuki3, miura@cs.kobe-u.ac.jp, Matsuda, Kohei3, matsuda@cs.kobe-u.ac.jp, Nagata, Makoto3, nagata@cs.kobe-u.ac.jp, Bhasin, Shivam4, sbhasin@ntu.edu.sg, Mathieu, Yves5, yves.mathieu@telecom-paristech.fr, Graba, Tarik5, tarik.graba@telecom-paristech.fr, Danger, Jean-Luc5, jean-luc.danger@telecom-paristech.fr |
| Source: | IEEE Transactions on Computers; Apr2020, Vol. 69 Issue 4, p534-548, 15p |
| Database: | Applied Science & Technology Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: aci DbLabel: Applied Science & Technology Source An: 142235961 AccessLevel: 2 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AU" term="%22Ueno%2C+Rei%22">Ueno, Rei</searchLink><relatesTo>1</relatesTo>, <i>ueno@riec.tohoku.ac.jp</i><br /><searchLink fieldCode="AU" term="%22Homma%2C+Naofumi%22">Homma, Naofumi</searchLink><relatesTo>1</relatesTo>, <i>homma@riec.tohoku.ac.jp</i><br /><searchLink fieldCode="AU" term="%22Morioka%2C+Sumio%22">Morioka, Sumio</searchLink><relatesTo>2</relatesTo>, <i>morioka@fb3.so-net.ne.jp</i><br /><searchLink fieldCode="AU" term="%22Miura%2C+Noriyuki%22">Miura, Noriyuki</searchLink><relatesTo>3</relatesTo>, <i>miura@cs.kobe-u.ac.jp</i><br /><searchLink fieldCode="AU" term="%22Matsuda%2C+Kohei%22">Matsuda, Kohei</searchLink><relatesTo>3</relatesTo>, <i>matsuda@cs.kobe-u.ac.jp</i><br /><searchLink fieldCode="AU" term="%22Nagata%2C+Makoto%22">Nagata, Makoto</searchLink><relatesTo>3</relatesTo>, <i>nagata@cs.kobe-u.ac.jp</i><br /><searchLink fieldCode="AU" term="%22Bhasin%2C+Shivam%22">Bhasin, Shivam</searchLink><relatesTo>4</relatesTo>, <i>sbhasin@ntu.edu.sg</i><br /><searchLink fieldCode="AU" term="%22Mathieu%2C+Yves%22">Mathieu, Yves</searchLink><relatesTo>5</relatesTo>, <i>yves.mathieu@telecom-paristech.fr</i><br /><searchLink fieldCode="AU" term="%22Graba%2C+Tarik%22">Graba, Tarik</searchLink><relatesTo>5</relatesTo>, <i>tarik.graba@telecom-paristech.fr</i><br /><searchLink fieldCode="AU" term="%22Danger%2C+Jean-Luc%22">Danger, Jean-Luc</searchLink><relatesTo>5</relatesTo>, <i>jean-luc.danger@telecom-paristech.fr</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computers%22">IEEE Transactions on Computers</searchLink>; Apr2020, Vol. 69 Issue 4, p534-548, 15p |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=142235961 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TC.2019.2957355 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 15 StartPage: 534 Titles: – TitleFull: High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ueno, Rei – PersonEntity: Name: NameFull: Homma, Naofumi – PersonEntity: Name: NameFull: Morioka, Sumio – PersonEntity: Name: NameFull: Miura, Noriyuki – PersonEntity: Name: NameFull: Matsuda, Kohei – PersonEntity: Name: NameFull: Nagata, Makoto – PersonEntity: Name: NameFull: Bhasin, Shivam – PersonEntity: Name: NameFull: Mathieu, Yves – PersonEntity: Name: NameFull: Graba, Tarik – PersonEntity: Name: NameFull: Danger, Jean-Luc IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 04 Text: Apr2020 Type: published Y: 2020 Identifiers: – Type: issn-print Value: 00189340 Numbering: – Type: volume Value: 69 – Type: issue Value: 4 Titles: – TitleFull: IEEE Transactions on Computers Type: main |
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