A high-performance framework for a network programmable packet processor using P4 and FPGA.
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| Title: | A high-performance framework for a network programmable packet processor using P4 and FPGA. |
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| Authors: | Yazdinejad, Abbas1, abbas@cybersciencelab.org, Parizi, Reza M.2, rparizi1@kennesaw.edu, Bohlooli, Ali3, bohlooli@eng.ui.ac.ir, Dehghantanha, Ali1, adehghan@uoguelph.ca, Choo, Kim-Kwang Raymond1,4, raymond.choo@fulbrightmail.org |
| Source: | Journal of Network & Computer Applications; Apr2020, Vol. 156, pN.PAG-N.PAG, 1p |
| Database: | Applied Science & Technology Source |
| ISSN: | 10848045 |
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| DOI: | 10.1016/j.jnca.2020.102564 |
