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A high-performance framework for a network programmable packet processor using P4 and FPGA.

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Title: A high-performance framework for a network programmable packet processor using P4 and FPGA.
Authors: Yazdinejad, Abbas1, abbas@cybersciencelab.org, Parizi, Reza M.2, rparizi1@kennesaw.edu, Bohlooli, Ali3, bohlooli@eng.ui.ac.ir, Dehghantanha, Ali1, adehghan@uoguelph.ca, Choo, Kim-Kwang Raymond1,4, raymond.choo@fulbrightmail.org
Source: Journal of Network & Computer Applications; Apr2020, Vol. 156, pN.PAG-N.PAG, 1p
Database: Applied Science & Technology Source
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  Availability: 0
Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 142320228
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: A high-performance framework for a network programmable packet processor using P4 and FPGA.
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Network+%26+Computer+Applications%22">Journal of Network & Computer Applications</searchLink>; Apr2020, Vol. 156, pN.PAG-N.PAG, 1p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=142320228
RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1016/j.jnca.2020.102564
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      – Code: eng
        Text: English
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        PageCount: 1
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      – TitleFull: A high-performance framework for a network programmable packet processor using P4 and FPGA.
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            NameFull: Yazdinejad, Abbas
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            NameFull: Parizi, Reza M.
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            NameFull: Bohlooli, Ali
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            NameFull: Choo, Kim-Kwang Raymond
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            – D: 15
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              Text: Apr2020
              Type: published
              Y: 2020
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              Value: 156
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