Optimizing FPGA Logic Block Architectures for Arithmetic.
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| Title: | Optimizing FPGA Logic Block Architectures for Arithmetic. |
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| Authors: | Murray, Kevin E.1, k.murray@mail.utoronto.ca, Luu, Jason1, Walker, Matthew J. P.1, McCullough, Conor2, Wang, Sen2, Huda, Safeen1, Yan, Bo2, Chiasson, Charles1, Kent, Kenneth B.2, Anderson, Jason1, Rose, Jonathan1, Betz, Vaughn1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Jun2020, Vol. 28 Issue 6, p1378-1391, 14p |
| Database: | Applied Science & Technology Source |
| ISSN: | 10638210 |
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| DOI: | 10.1109/TVLSI.2020.2965772 |
