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CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication.

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Bibliographic Details
Title:	CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication.
Authors:	Vikram, Abhishek¹, abvikram@ieee.org, Agarwal, Vineeta¹, vineeta@mnnit.ac.in, Agarwal, Anshul², anshul@nitdelhi.ac.in
Source:	IETE Journal of Research; Sep-Oct2020, Vol. 66 Issue 5, p677-684, 8p
Database:	Applied Science & Technology Source
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Description
ISSN:	03772063
DOI:	10.1080/03772063.2018.1517617