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Distributed Self-Clock: A Suitable Architecture for SFQ Circuits.

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Title: Distributed Self-Clock: A Suitable Architecture for SFQ Circuits.
Authors: Yang, Jia-Hong1, Tang, Guang-Ming1, tangguangming@ict.ac.cn, Zheng, Xiang-Yu1, Ye, Xiao-Chun1, Fan, Dong-Rui1, Zhang, Zhi-Min1, Sun, Ning-Hui1
Source: IEEE Transactions on Applied Superconductivity; Oct2020, Vol. 30 Issue 7, p1-7, 7p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 147319406
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: Distributed Self-Clock: A Suitable Architecture for SFQ Circuits.
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        Value: 10.1109/TASC.2020.3007175
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        Text: English
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        PageCount: 7
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      – TitleFull: Distributed Self-Clock: A Suitable Architecture for SFQ Circuits.
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            NameFull: Fan, Dong-Rui
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            – D: 01
              M: 10
              Text: Oct2020
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              Y: 2020
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