P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter.
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| Title: | P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter. |
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| Authors: | Basha, S. Mahaboob1, smb.ece@rmkec.ac.in, Arun, A.2, Srinath, B.3, Yuvaraj, S.3, Magesh, V.4, Bhuvaneswari, V.5 |
| Source: | Analog Integrated Circuits & Signal Processing; Jun2022, Vol. 111 Issue 3, p441-450, 10p |
| Database: | Applied Science & Technology Source |
| ISSN: | 09251030 |
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| DOI: | 10.1007/s10470-022-01999-z |
