P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter.
Saved in:
| Title: | P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter. |
|---|---|
| Authors: | Basha, S. Mahaboob1, smb.ece@rmkec.ac.in, Arun, A.2, Srinath, B.3, Yuvaraj, S.3, Magesh, V.4, Bhuvaneswari, V.5 |
| Source: | Analog Integrated Circuits & Signal Processing; Jun2022, Vol. 111 Issue 3, p441-450, 10p |
| Database: | Applied Science & Technology Source |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: aci DbLabel: Applied Science & Technology Source An: 156706955 AccessLevel: 2 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AU" term="%22Basha%2C+S%2E+Mahaboob%22">Basha, S. Mahaboob</searchLink><relatesTo>1</relatesTo>, <i>smb.ece@rmkec.ac.in</i><br /><searchLink fieldCode="AU" term="%22Arun%2C+A%2E%22">Arun, A.</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AU" term="%22Srinath%2C+B%2E%22">Srinath, B.</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AU" term="%22Yuvaraj%2C+S%2E%22">Yuvaraj, S.</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AU" term="%22Magesh%2C+V%2E%22">Magesh, V.</searchLink><relatesTo>4</relatesTo><br /><searchLink fieldCode="AU" term="%22Bhuvaneswari%2C+V%2E%22">Bhuvaneswari, V.</searchLink><relatesTo>5</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Analog+Integrated+Circuits+%26+Signal+Processing%22">Analog Integrated Circuits & Signal Processing</searchLink>; Jun2022, Vol. 111 Issue 3, p441-450, 10p |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=156706955 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s10470-022-01999-z Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 441 Titles: – TitleFull: P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Basha, S. Mahaboob – PersonEntity: Name: NameFull: Arun, A. – PersonEntity: Name: NameFull: Srinath, B. – PersonEntity: Name: NameFull: Yuvaraj, S. – PersonEntity: Name: NameFull: Magesh, V. – PersonEntity: Name: NameFull: Bhuvaneswari, V. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun2022 Type: published Y: 2022 Identifiers: – Type: issn-print Value: 09251030 Numbering: – Type: volume Value: 111 – Type: issue Value: 3 Titles: – TitleFull: Analog Integrated Circuits & Signal Processing Type: main |
| ResultId | 1 |