APA (7th ed.) Citation

Chattopadhyay, A., & Bose, C. (2024). Investigation of Core–Shell Junctionless Gate-Stack DG-FET in Low-Power Applications Using Charge-Based Modeling. Journal of Electronic Materials, 53(1), 157. https://doi.org/10.1007/s11664-023-10742-x

Chicago Style (17th ed.) Citation

Chattopadhyay, Ankush, and Chayanika Bose. "Investigation of Core–Shell Junctionless Gate-Stack DG-FET in Low-Power Applications Using Charge-Based Modeling." Journal of Electronic Materials 53, no. 1 (2024): 157. https://doi.org/10.1007/s11664-023-10742-x.

MLA (9th ed.) Citation

Chattopadhyay, Ankush, and Chayanika Bose. "Investigation of Core–Shell Junctionless Gate-Stack DG-FET in Low-Power Applications Using Charge-Based Modeling." Journal of Electronic Materials, vol. 53, no. 1, 2024, p. 157, https://doi.org/10.1007/s11664-023-10742-x.