A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay.
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| Title: | A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay. |
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| Authors: | Sharma, Buddhi Prakash1, p20200414@pilani.bits-pilani.ac.in, Rajagopal, Rajeev1, f20201237@pilani.bits-pilani.ac.in, Sekhar, Ranjeeth1, f20200316@pilani.bits-pilani.ac.in, Gupta, Anu1, anug@pilani.bits-pilani.ac.in, Shekhar, Chandra1, chandra.shekhar@pilani.bits-pilani.ac.in |
| Source: | Journal of Circuits, Systems & Computers; 1/30/2025, Vol. 34 Issue 2, p1-24, 24p |
| Database: | Applied Science & Technology Source |
| ISSN: | 02181266 |
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| DOI: | 10.1142/S021812662550063X |
