APA (7th ed.) Citation

Oh, S. H., Hong, T. Y., Kim, S. E., Park, J. K., & Hong, S. K. (2025). Layout Design Strategies for Scaling Down Semiconductor Systems Based on Current Flow Analysis in Interconnect. Applied Sciences (2076-3417), 15(7), 3944. https://doi.org/10.3390/app15073944

Chicago Style (17th ed.) Citation

Oh, Seung Hwan, Tae Yeong Hong, Sarah Eunkyung Kim, Jong Kyung Park, and Seul Ki Hong. "Layout Design Strategies for Scaling Down Semiconductor Systems Based on Current Flow Analysis in Interconnect." Applied Sciences (2076-3417) 15, no. 7 (2025): 3944. https://doi.org/10.3390/app15073944.

MLA (9th ed.) Citation

Oh, Seung Hwan, et al. "Layout Design Strategies for Scaling Down Semiconductor Systems Based on Current Flow Analysis in Interconnect." Applied Sciences (2076-3417), vol. 15, no. 7, 2025, p. 3944, https://doi.org/10.3390/app15073944.