Layout Design Strategies for Scaling Down Semiconductor Systems Based on Current Flow Analysis in Interconnect.
Saved in:
| Title: | Layout Design Strategies for Scaling Down Semiconductor Systems Based on Current Flow Analysis in Interconnect. |
|---|---|
| Authors: | Oh, Seung Hwan1, Hong, Tae Yeong1, Kim, Sarah Eunkyung1, Park, Jong Kyung1, Hong, Seul Ki1, skhong@seoultech.ac.kr |
| Source: | Applied Sciences (2076-3417); Apr2025, Vol. 15 Issue 7, p3944, 12p |
| Database: | Applied Science & Technology Source |
|
Full text is not displayed to guests.
Login for full access.
|
|
Be the first to leave a comment!
