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A 6 bit and 500 MS/s hybrid ADC with energy efficient CDAC switching scheme.

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Title: A 6 bit and 500 MS/s hybrid ADC with energy efficient CDAC switching scheme.
Authors: Balasubramanian, Dinesh Kumar1, sbdineshkumarbalu@gmail.com, Gupta, Navneet2, navneet.gupta@ieee.org, Amara, Amara2, aamara@ieee.org, Shrimali, Hitesh1, hitesh@iitmandi.ac.in
Source: Analog Integrated Circuits & Signal Processing; Jul2025, Vol. 124 Issue 1, p1-13, 13p
Database: Applied Science & Technology Source
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  Availability: 0
Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 185709464
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: <searchLink fieldCode="JN" term="%22Analog+Integrated+Circuits+%26+Signal+Processing%22">Analog Integrated Circuits & Signal Processing</searchLink>; Jul2025, Vol. 124 Issue 1, p1-13, 13p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=185709464
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      – Type: doi
        Value: 10.1007/s10470-025-02408-x
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      – Code: eng
        Text: English
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      – TitleFull: A 6 bit and 500 MS/s hybrid ADC with energy efficient CDAC switching scheme.
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            NameFull: Balasubramanian, Dinesh Kumar
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              Text: Jul2025
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              Y: 2025
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              Value: 124
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