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Design and Realization of Novel Dual-Input Logic Gates using Virtual Doped Junctionless Double-Gate TFETs.

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Title: Design and Realization of Novel Dual-Input Logic Gates using Virtual Doped Junctionless Double-Gate TFETs.
Authors: Sharma, Arun Kumar1, 2020rec9017@mnit.ac.in, Kumar, Ritik1, 2022pev5404@mnit.ac.in, Gopal, Girdhar2, 2019rec9550@mnit.ac.in, Johar, Arun Kishor3, johar.arun@gmail.com, Varma, Tarun1, tarun@mnit.ac.in
Source: Journal of Electronic Materials; Jul2025, Vol. 54 Issue 7, p5901-5917, 17p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 185782371
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PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Design and Realization of Novel Dual-Input Logic Gates using Virtual Doped Junctionless Double-Gate TFETs.
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  Data: <searchLink fieldCode="AU" term="%22Sharma%2C+Arun+Kumar%22">Sharma, Arun Kumar</searchLink><relatesTo>1</relatesTo>, <i>2020rec9017@mnit.ac.in</i><br /><searchLink fieldCode="AU" term="%22Kumar%2C+Ritik%22">Kumar, Ritik</searchLink><relatesTo>1</relatesTo>, <i>2022pev5404@mnit.ac.in</i><br /><searchLink fieldCode="AU" term="%22Gopal%2C+Girdhar%22">Gopal, Girdhar</searchLink><relatesTo>2</relatesTo>, <i>2019rec9550@mnit.ac.in</i><br /><searchLink fieldCode="AU" term="%22Johar%2C+Arun+Kishor%22">Johar, Arun Kishor</searchLink><relatesTo>3</relatesTo>, <i>johar.arun@gmail.com</i><br /><searchLink fieldCode="AU" term="%22Varma%2C+Tarun%22">Varma, Tarun</searchLink><relatesTo>1</relatesTo>, <i>tarun@mnit.ac.in</i>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Electronic+Materials%22">Journal of Electronic Materials</searchLink>; Jul2025, Vol. 54 Issue 7, p5901-5917, 17p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=185782371
RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1007/s11664-025-12011-5
    Languages:
      – Code: eng
        Text: English
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      Pagination:
        PageCount: 17
        StartPage: 5901
    Titles:
      – TitleFull: Design and Realization of Novel Dual-Input Logic Gates using Virtual Doped Junctionless Double-Gate TFETs.
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      – PersonEntity:
          Name:
            NameFull: Sharma, Arun Kumar
      – PersonEntity:
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            NameFull: Kumar, Ritik
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            NameFull: Gopal, Girdhar
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            NameFull: Johar, Arun Kishor
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            NameFull: Varma, Tarun
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          Dates:
            – D: 01
              M: 07
              Text: Jul2025
              Type: published
              Y: 2025
          Identifiers:
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              Value: 03615235
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              Value: 54
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              Value: 7
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