A Novel and Efficient Left-to-Right Binary Adder Architecture for reduced Area and Power Metrics in VLSI Design.
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| Title: | A Novel and Efficient Left-to-Right Binary Adder Architecture for reduced Area and Power Metrics in VLSI Design. |
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| Authors: | Anuradha, M. G.1, anuradhamg@jssateb.ac.in, Kumar, R. Arun2, arun1979arun@gmail.com |
| Source: | Engineering, Technology & Applied Science Research; Jun2025, Vol. 15 Issue 3, p22629-22635, 7p |
| Database: | Applied Science & Technology Source |
| ISSN: | 22414487 |
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| DOI: | 10.48084/etasr.9840 |
