Design of compressor-based multipliers using simulated annealing for arithmetic logic unit.
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| Title: | Design of compressor-based multipliers using simulated annealing for arithmetic logic unit. |
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| Authors: | Pavitra, Y. J.1, pavitra.yj@pes.edu, Manikandan, J.1 |
| Source: | Neural Computing & Applications; Nov2025, Vol. 37 Issue 33, p27747-27757, 11p |
| Database: | Applied Science & Technology Source |
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| ISSN: | 09410643 |
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| DOI: | 10.1007/s00521-025-10981-5 |
