Hardware efficient multiplier design for deep learning processing unit.
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| Title: | Hardware efficient multiplier design for deep learning processing unit. |
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| Authors: | V., Jean Shilpa1, jeanshilpa@crescent.education, R., Anitha1, r.anitha@crescent.education, S., Anusooya1, anusooya@crescent.education, P. K., Jawahar1, jawahar@crescent.education, E., Nithesh1, nnithesh542@gmail.com, S., Sairamsiva1, sairamsiva05@gmail.com, K., Syed Rahaman1, syedrahman2004@gmail.com |
| Source: | International Journal of Electrical & Computer Engineering (2088-8708); Dec2025, Vol. 15 Issue 6, p5205-5214, 10p |
| Database: | Applied Science & Technology Source |
| ISSN: | 20888708 |
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| DOI: | 10.11591/ijece.v15i6.pp5205-5214 |
