APA (7th ed.) Citation

V., J. S., R., A., S., A., P. K., J., E., N., S., S., & K., S. R. (2025). Hardware efficient multiplier design for deep learning processing unit. International Journal of Electrical & Computer Engineering (2088-8708), 15(6), 5205. https://doi.org/10.11591/ijece.v15i6.pp5205-5214

Chicago Style (17th ed.) Citation

V., Jean Shilpa, Anitha R., Anusooya S., Jawahar P. K., Nithesh E., Sairamsiva S., and Syed Rahaman K. "Hardware Efficient Multiplier Design for Deep Learning Processing Unit." International Journal of Electrical & Computer Engineering (2088-8708) 15, no. 6 (2025): 5205. https://doi.org/10.11591/ijece.v15i6.pp5205-5214.

MLA (9th ed.) Citation

V., Jean Shilpa, et al. "Hardware Efficient Multiplier Design for Deep Learning Processing Unit." International Journal of Electrical & Computer Engineering (2088-8708), vol. 15, no. 6, 2025, p. 5205, https://doi.org/10.11591/ijece.v15i6.pp5205-5214.