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SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification.

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Bibliographic Details
Title: SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification.
Authors: Cummings, Clifford E.1, cliffc@sunburst-design.com
Source: DAC: Annual ACM/IEEE Design Automation Conference; 2008, p231-236, 6p, 1 Diagram, 1 Chart
Database: Applied Science & Technology Source
Description
ISSN:0738100X