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An offset reduction technique for use with CMOS integrated comparators and amplifiers.

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Bibliographic Details
Title: An offset reduction technique for use with CMOS integrated comparators and amplifiers.
Authors: Atherton, James H., Simmonds, H. Thomas
Source: IEEE Journal of Solid-State Circuits; August 1992, Vol. 27, p1168-1175, 8p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 500021884
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: An offset reduction technique for use with CMOS integrated comparators and amplifiers.
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  Data: <searchLink fieldCode="AU" term="%22Atherton%2C+James+H%2E%22">Atherton, James H.</searchLink><br /><searchLink fieldCode="AU" term="%22Simmonds%2C+H%2E+Thomas%22">Simmonds, H. Thomas</searchLink>
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        Value: 10.1109/4.148325
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      – Code: eng
        Text: English
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        PageCount: 8
        StartPage: 1168
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      – TitleFull: An offset reduction technique for use with CMOS integrated comparators and amplifiers.
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            NameFull: Atherton, James H.
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            NameFull: Simmonds, H. Thomas
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              Text: August 1992
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              Y: 1992
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              Value: 27
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