The impact of iron, copper, and calcium contamination of silicon surfaces on the yield of a MOS DRAM test process.
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| Title: | The impact of iron, copper, and calcium contamination of silicon surfaces on the yield of a MOS DRAM test process. |
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| Authors: | Burte, E. P., Aderhold, W. |
| Source: | Solid-State Electronics; July 1997, Vol. 41, p1021-1025, 5p |
| Database: | Applied Science & Technology Source |
| ISSN: | 00381101 |
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| DOI: | 10.1016/S0038-1101(97)00016-6 |
