APA (7th ed.) Citation

Burte, E. P., & Aderhold, W. (1997). The impact of iron, copper, and calcium contamination of silicon surfaces on the yield of a MOS DRAM test process. Solid-State Electronics, 41, 1021. https://doi.org/10.1016/S0038-1101(97)00016-6

Chicago Style (17th ed.) Citation

Burte, E. P., and W. Aderhold. "The Impact of Iron, Copper, and Calcium Contamination of Silicon Surfaces on the Yield of a MOS DRAM Test Process." Solid-State Electronics 41 (1997): 1021. https://doi.org/10.1016/S0038-1101(97)00016-6.

MLA (9th ed.) Citation

Burte, E. P., and W. Aderhold. "The Impact of Iron, Copper, and Calcium Contamination of Silicon Surfaces on the Yield of a MOS DRAM Test Process." Solid-State Electronics, vol. 41, 1997, p. 1021, https://doi.org/10.1016/S0038-1101(97)00016-6.