Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits.

Saved in:
Bibliographic Details
Title: Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits.
Authors: Taskin, Baris, Kourtev, Ivan S.
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; January 2004, Vol. 12 Issue 1, p12-27, 16p
Database: Applied Science & Technology Source
Description
ISSN:10638210
DOI:10.1109/TVLSI.2003.820525