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Reliability Improvement of Logic and Clock Paths in Power-Efficient Designs.

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Bibliographic Details
Title: Reliability Improvement of Logic and Clock Paths in Power-Efficient Designs.
Authors: ARASU, SENTHIL1, NOURANI, MEHRDAD1, nourani@utdallas.edu, REDDY, VIJAY2, CARULLI, JOHN M.2, KAPILA, GAUTAM2, MIN CHEN2
Source: ACM Journal on Emerging Technologies in Computing Systems; Jan2014, Vol. 10 Issue 1, p3:1-3:23, 23p
Database: Applied Science & Technology Source
Description
ISSN:15504832
DOI:10.1145/2543749.2543751