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Reliability Improvement of Logic and Clock Paths in Power-Efficient Designs.

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Title: Reliability Improvement of Logic and Clock Paths in Power-Efficient Designs.
Authors: ARASU, SENTHIL1, NOURANI, MEHRDAD1, nourani@utdallas.edu, REDDY, VIJAY2, CARULLI, JOHN M.2, KAPILA, GAUTAM2, MIN CHEN2
Source: ACM Journal on Emerging Technologies in Computing Systems; Jan2014, Vol. 10 Issue 1, p3:1-3:23, 23p
Database: Applied Science & Technology Source
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PubType: Academic Journal
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PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=93981747
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        Value: 10.1145/2543749.2543751
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        Text: English
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              Text: Jan2014
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