Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity.
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| Title: | Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity. |
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| Authors: | Kaixing Cheng1 chengkaixingme@gmail.com, Zhongqiang Luo1 zhongqiangluo@gmail.com, Xingzhong Xiong1 xzxiong@suse.edu.cn, Xiaohan Wei1 weixiaohans@163.com |
| Source: | International Journal of Electronics & Telecommunications. 2021, Vol. 67 Issue 3, p385-394. 10p. |
| Database: | Academic Search Ultimate |
| ISSN: | 20818491 |
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| DOI: | 10.24425/ijet.2021.137824 |
