APA (7th ed.) Citation

Cheng, K., Luo, Z., Xiong, X., & Wei, X. (2021). Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity. International Journal of Electronics & Telecommunications, 67(3), 385. https://doi.org/10.24425/ijet.2021.137824

Chicago Style (17th ed.) Citation

Cheng, Kaixing, Zhongqiang Luo, Xingzhong Xiong, and Xiaohan Wei. "Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity." International Journal of Electronics & Telecommunications 67, no. 3 (2021): 385. https://doi.org/10.24425/ijet.2021.137824.

MLA (9th ed.) Citation

Cheng, Kaixing, et al. "Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity." International Journal of Electronics & Telecommunications, vol. 67, no. 3, 2021, p. 385, https://doi.org/10.24425/ijet.2021.137824.