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Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity.

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Title: Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity.
Authors: Kaixing Cheng1 chengkaixingme@gmail.com, Zhongqiang Luo1 zhongqiangluo@gmail.com, Xingzhong Xiong1 xzxiong@suse.edu.cn, Xiaohan Wei1 weixiaohans@163.com
Source: International Journal of Electronics & Telecommunications. 2021, Vol. 67 Issue 3, p385-394. 10p.
Database: Academic Search Ultimate
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PubType: Academic Journal
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  Data: Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity.
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  Data: <searchLink fieldCode="AR" term="%22Kaixing+Cheng%22">Kaixing Cheng</searchLink><relatesTo>1</relatesTo><i> chengkaixingme@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Zhongqiang+Luo%22">Zhongqiang Luo</searchLink><relatesTo>1</relatesTo><i> zhongqiangluo@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Xingzhong+Xiong%22">Xingzhong Xiong</searchLink><relatesTo>1</relatesTo><i> xzxiong@suse.edu.cn</i><br /><searchLink fieldCode="AR" term="%22Xiaohan+Wei%22">Xiaohan Wei</searchLink><relatesTo>1</relatesTo><i> weixiaohans@163.com</i>
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  Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Electronics+%26+Telecommunications%22">International Journal of Electronics & Telecommunications</searchLink>. 2021, Vol. 67 Issue 3, p385-394. 10p.
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=asn&AN=153004135
RecordInfo BibRecord:
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      – Type: doi
        Value: 10.24425/ijet.2021.137824
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      – Code: eng
        Text: English
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        PageCount: 10
        StartPage: 385
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      – TitleFull: Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity.
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            NameFull: Kaixing Cheng
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            NameFull: Zhongqiang Luo
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            NameFull: Xingzhong Xiong
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              Text: 2021
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              Value: 67
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            – TitleFull: International Journal of Electronics & Telecommunications
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