Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits.

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Title: Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits.
Authors: Smaani, Billel1 b.smaani@univ-boumerdes.dz, Meraihi, Yacin2 y.meraihi@univ-boumerdes.dz, Nafa, Fares2 f.nafa@univ-boumerdes.dz, Benlatreche, Mohamed Salah3 msbenlatreche@univ-boumerdes.dz, Akroum, Hamza4 akroum@gmail.com, Latreche, Saida5 latreche.saida@gmail.com
Source: International Journal of Electronics & Telecommunications. 2021, Vol. 67 Issue 4, p609-614. 6p.
Database: Academic Search Ultimate
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An: 154160343
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  Data: Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits.
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  Data: <searchLink fieldCode="AR" term="%22Smaani%2C+Billel%22">Smaani, Billel</searchLink><relatesTo>1</relatesTo><i> b.smaani@univ-boumerdes.dz</i><br /><searchLink fieldCode="AR" term="%22Meraihi%2C+Yacin%22">Meraihi, Yacin</searchLink><relatesTo>2</relatesTo><i> y.meraihi@univ-boumerdes.dz</i><br /><searchLink fieldCode="AR" term="%22Nafa%2C+Fares%22">Nafa, Fares</searchLink><relatesTo>2</relatesTo><i> f.nafa@univ-boumerdes.dz</i><br /><searchLink fieldCode="AR" term="%22Benlatreche%2C+Mohamed+Salah%22">Benlatreche, Mohamed Salah</searchLink><relatesTo>3</relatesTo><i> msbenlatreche@univ-boumerdes.dz</i><br /><searchLink fieldCode="AR" term="%22Akroum%2C+Hamza%22">Akroum, Hamza</searchLink><relatesTo>4</relatesTo><i> akroum@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Latreche%2C+Saida%22">Latreche, Saida</searchLink><relatesTo>5</relatesTo><i> latreche.saida@gmail.com</i>
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  Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Electronics+%26+Telecommunications%22">International Journal of Electronics & Telecommunications</searchLink>. 2021, Vol. 67 Issue 4, p609-614. 6p.
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=asn&AN=154160343
RecordInfo BibRecord:
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        Value: 10.24425/ijet.2021.137853
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      – Code: eng
        Text: English
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        PageCount: 6
        StartPage: 609
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      – TitleFull: Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits.
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            NameFull: Smaani, Billel
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            NameFull: Meraihi, Yacin
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            NameFull: Nafa, Fares
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            NameFull: Benlatreche, Mohamed Salah
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            NameFull: Akroum, Hamza
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              Text: 2021
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              Value: 67
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            – TitleFull: International Journal of Electronics & Telecommunications
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