A Picosecond Delay Generator Optimized by Layout and Routing Based on FPGA.
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| Title: | A Picosecond Delay Generator Optimized by Layout and Routing Based on FPGA. |
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| Authors: | Zhu, Min1,2 (AUTHOR) zhumin@hit.edu.cn, Cui, Tang1 (AUTHOR) 22s006055@stu.hit.edu.cn, Qi, Xihan1 (AUTHOR), Gao, Qiang3 (AUTHOR) gaoq@hit.edu.cn |
| Source: | Sensors (14248220). Jul2023, Vol. 23 Issue 13, p6144. 16p. |
| Database: | Academic Search Ultimate |
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| ISSN: | 14248220 |
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| DOI: | 10.3390/s23136144 |
