APA (7th ed.) Citation

Varghese, A., Santhosh, S., & Verghese, S. (2026). A novel framework for automated configuration-driven verilog memory model generation and standardized UVM based verification with integrated testing. AIP Conference Proceedings, 3341(1), 1. https://doi.org/10.1063/5.0317162

Chicago Style (17th ed.) Citation

Varghese, Anand, Sachin Santhosh, and Sam Verghese. "A Novel Framework for Automated Configuration-driven Verilog Memory Model Generation and Standardized UVM Based Verification with Integrated Testing." AIP Conference Proceedings 3341, no. 1 (2026): 1. https://doi.org/10.1063/5.0317162.

MLA (9th ed.) Citation

Varghese, Anand, et al. "A Novel Framework for Automated Configuration-driven Verilog Memory Model Generation and Standardized UVM Based Verification with Integrated Testing." AIP Conference Proceedings, vol. 3341, no. 1, 2026, p. 1, https://doi.org/10.1063/5.0317162.