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Chip design flow of 6T, 7T, 8T and 9T static random access memory using VLSI development tool.

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Title: Chip design flow of 6T, 7T, 8T and 9T static random access memory using VLSI development tool.
Authors: Katru, Raju1 (AUTHOR) rajukatru2005@gmail.com, Raghavaiah, B.2 (AUTHOR) raghavaece39@gmail.com, Salauddin, Md.3 (AUTHOR) salal.vlsi@gmail.com, Rao, S. Jagan Mohan2 (AUTHOR) jaganmohanrs@rcee.ac.in, Babu, M. Renu4 (AUTHOR) renubabum@tkrec.ac.in, Kumar, J. Prashanth2 (AUTHOR)
Source: AIP Conference Proceedings. 2026, Vol. 3376 Issue 1, p1-8. 8p.
Database: Academic Search Ultimate
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Header DbId: asn
DbLabel: Academic Search Ultimate
An: 192845782
AccessLevel: 2
PubType: Conference
PubTypeId: conference
PreciseRelevancyScore: 0
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  Data: Chip design flow of 6T, 7T, 8T and 9T static random access memory using VLSI development tool.
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  Data: <searchLink fieldCode="JN" term="%22AIP+Conference+Proceedings%22">AIP Conference Proceedings</searchLink>. 2026, Vol. 3376 Issue 1, p1-8. 8p.
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=asn&AN=192845782
RecordInfo BibRecord:
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        Value: 10.1063/5.0330139
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      – Code: eng
        Text: English
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        PageCount: 8
        StartPage: 1
    Titles:
      – TitleFull: Chip design flow of 6T, 7T, 8T and 9T static random access memory using VLSI development tool.
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            NameFull: Katru, Raju
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            NameFull: Raghavaiah, B.
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            NameFull: Rao, S. Jagan Mohan
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            NameFull: Babu, M. Renu
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            NameFull: Kumar, J. Prashanth
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            – D: 08
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              Text: 2026
              Type: published
              Y: 2026
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